Implementing electric circuits involves connecting isolated devices or electronic components through specific electrical paths. When fabricating integrated circuits from semiconductor materials, such as silicon, it must therefore be possible to isolate devices built into the substrate from one another. Such devices are subsequently electrically interconnected to create the specific circuit configurations desired.
A variety of techniques have been developed to isolate devices in integrated circuits. Different integrated circuit types can require somewhat different isolation requirements. For example, PMOS and NMOS integrated circuits require an isolation structure that prevents the establishment of parasitic channels between adjacent transistor devices. MOS transistors are inherently self-isolated.
As long as the source-substrate and drain-substrate pn junctions are held at reverse bias in MOS transistors, the drain current (I.sub.D) should only be due to current flow from source to drain through a channel under the gate. This further implies that no significant current between adjacent MOS devices should exist if no channels exist between them. However, the method by which the components of an integrated circuit are interconnected involves the fabrication of conductive lines that run across oxide in the regions between the transistors, typically referred to as field oxide or field regions. Unfortunately, these conductive lines have a tendency to form gates of parasitic MOS transistors, with the oxide beneath them forming a gate oxide and the diffused regions of separate transistors adjacent the field regions acting as parasitic sources and drains. The threshold voltage of such parasitic transistors is kept higher than any possible operating voltage so that spurious channels will not be inadvertently formed between transistor devices. Two techniques for increasing the threshold voltage are increasing the field-oxide thickness and raising the doping concentration of the bulk substrate area beneath the field oxide.
Typical prior art isolation technology is described with reference to FIGS. 1 and 2. Referring first to FIG. 1, a semiconductor wafer fragment 10 is comprised of a bulk monocrystalline silicon substrate 12 and an isolating field oxide region 14 positioned between a pair of field effect transistor devices 16 and 18. Such transistors each comprise respective gate constructions 20, composed of a conductive portion 21, an underlying gate dielectric layer 22, and opposing insulating sidewall spacers 23. Each transistor is provided with a pair of electrically conductive n+ source/drain diffusion regions 24 and 25. Example dopant concentration for regions 24 and 25 is 1.times.10.sup.20 ions/cm.sup.3 or greater. Bulk substrate or well area 12 is provided to a p-concentration, such as 1.times.10.sup.15 ions/cm.sup.3. Transistors 16 and 18 are also provided with n- lightly doped drain (LDD) regions 26. Example concentration for regions 26 is 1.times.10.sup.17 ions/cm.sup.3. Immediately beneath field oxide region 14, an implant has been conducted to provide a higher concentration of p-type material, indicated by the plurality of "+" symbols therebeneath. Such effectively raises the threshold voltage for a preventing a parasitic transistor from forming beneath oxide 14 utilizing the adjacent regions 24 and 25 as parasitic sources and drains.
FIG. 2 illustrates an alternate prior art isolation process, referred to as buried-oxide (BOX) isolation technology. Like numerals are utilized from the first described embodiment where appropriate, with differences being indicated with different numerals or with the suffix "a". Buried-oxide isolation technology typically uses shallow trenches 28 formed within bulk substrate 12 which are refilled with a chemical vapor deposited SiO.sub.2 layer 30. This layer is then etched back to yield the illustrated planar upper surface 31.
This invention comprises improved techniques for providing electrical isolation between adjacent semiconductor diffusion regions of different field effect transistors.